Verilog HDL was first introduced in 1984 by Prabhu Goel and Phil Moorby. Back then, it was a propriety HDL and was maintained by Gateway Design Automation Inc. Till 1990, a lot of revisions were released for the language. However, in 1990, Cadence Design System took over Gateway Design Automation Inc. Understanding the potential of this language, Cadence transferred it to the public domain with the name OVI (Open Verilog International).<\/span><\/p>\n In 2005, minor corrections of the language were published along with SystemVerilog, which is a superset of VHDL. In 2009, Verilog and SystemVerilog were merged and even today, this remains as one of the highly used languages for verification and IC design.<\/span><\/p>\n In this article, we will discuss the basics of Verilog HDL.<\/span><\/p>\n VHDL is the most commonly utilised Hardware Description Languages (HDL) due to its ease of circuit simulation. With this language, it is possible to use multiple abstractions such as data flow, structural, and behavioural code styles.\u00a0<\/span><\/p>\n And if you know a thing or two about digital circuits, you can know a lot about Verilog design.<\/span><\/p>\n Here\u2019s a simple example.<\/span><\/p>\n The circuit has two input ports and one output port, and the logic used is AND logic. The two inputs functionally use AND logic to give a single output.<\/span><\/p>\n Now, the description of this logic in Verilog is:<\/span><\/p>\n entity sample_1 is<\/span><\/i><\/p>\n \u00a0\u00a0\u00a0\u00a0Port (X: in STD_LOGIC;<\/span><\/i><\/p>\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Y: in STD_LOGIC;<\/span><\/i><\/p>\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Z: out STD_LOGIC);<\/span><\/i><\/p>\n end sample_1;<\/span><\/i><\/p>\n Verilog\u2019s syntax is simple, it starts by defining the module name with the <\/span>entity<\/span><\/i>, which concludes with the <\/span>end<\/span><\/i>. <\/span>STD_LOGIC<\/span><\/i> is a common data type used in Verilog.\u00a0<\/span><\/p>\n The first building block of VHDL is a module. It is a collection of design blocks at a lower level. Here, various elements of the design are grouped in a module which can be used at various instances in the design itself. This block starts with the <\/span>module<\/span><\/i> and concludes with the <\/span>endmodule<\/span><\/i>.<\/span><\/p>\n A module needs an interface to communicate, and this is provided by ports. The circuit environment can communicate with the module through ports. Take the IC chip, for instance. The <\/span>input<\/span><\/i> and <\/span>output<\/span><\/i> pins in this chip are ports.<\/span><\/p>\n The processes in VHDL are used inside the architecture. These processes execute sequentially. In the behavioural model, processes are extremely important. For a model to simulate effectively, all of its components should be described in one or multiple processes.<\/span><\/p>\n A signal assignment changes the waveform outputs. It can be used inside an architecture or process directly. Usually, we use either sequential or concurrent signal assignment.<\/span><\/p>\n For instance, a sequential assignment when present inside the process executes once the process ends.\u00a0<\/span><\/p>\n It is the highest abstraction level which defines the circuit based on its behaviour. If you know how your circuit will behave, you can design it using behavioural code style.<\/span><\/p>\n This code style is like the natural language processing of the circuit\u2019s functionality.<\/span><\/p>\n Structural code style is similar to assembly language as it uses logic gates to define the circuit\u2019s functionality. Designing a circuit with this code style matches the gate-level logic implementation.<\/span><\/p>\n The code style at this level defines the flow of data in the design components of the circuit. For instance, it uses Register Transfer Logic or RTL to define the circuit\u2019s functionality.\u00a0<\/span><\/p>\n The top-down approach builds the top-level block first and then identifies its sub-level blocks. These are divided till the leaf-level is reached.<\/span><\/p>\n The bottom-up approach is traditional, which means that the logic is defined at the gate-level. First, building blocks are identified, then these are constantly used to build bigger cells until we have the top-level block of the design.<\/span><\/p>\n In practice, the hybrid approach is utilised. The design architect defines the top-level block, the logic designer decides the structure of the top-level and sub-level blocks, and circuit designer defines the leaf-level blocks.<\/span><\/p>\n Conclusion\u00a0<\/span><\/p>\n Verilog HDL is an important part of circuit design. With highly complex circuit behaviour, Verilog allows designers to confide in the design by reducing the chances of failure. Further, it accelerates simulation which reduces the time-to-market. With all these benefits, it is impossible for the circuit designers to not use Verilog for hardware description and verification.\u00a0<\/span><\/p>\n","protected":false},"excerpt":{"rendered":" Using Verilog HDL in Programmable Logic Design: A Comprehensive Guide Verilog HDL was first introduced in 1984 by Prabhu Goel and Phil Moorby. Back then, it was a propriety HDL and was maintained by Gateway Design Automation Inc. Till 1990, a lot of revisions were released for the language. However, in 1990, Cadence Design System … <\/p>\nVerilog Basics<\/b><\/h3>\n
Building Blocks of VHDL<\/b><\/h3>\n
Modules<\/b><\/h4>\n
Ports<\/b><\/h4>\n
Processes<\/b><\/h4>\n
Assignments<\/b><\/h4>\n
VHDL Code Styles<\/b><\/h3>\n
Behavioural<\/b><\/h4>\n
Structural<\/b><\/h4>\n
Data Flow<\/b><\/h4>\n
VHDL Design Methodologies<\/b><\/h3>\n
Top-down<\/b><\/h4>\n
Bottom-up<\/b><\/h4>\n
Hybrid<\/b><\/h4>\n
Simulation vs Synthesis Model<\/b><\/h3>\n
\n\n
\n Simulation<\/b><\/td>\n Synthesis<\/b><\/td>\n<\/tr>\n \n Requires a sensitivity list<\/span><\/td>\n Uses logic such as combinational, large sensitive storage, and edge-sensitive storage.<\/span><\/td>\n<\/tr>\n \n Verifies circuit timing<\/span><\/td>\n Provides netlist as output.<\/span><\/td>\n<\/tr>\n \n Verifies circuit functionality<\/span><\/td>\n Converts VHDL description into components such as in FPGA or CPLD.<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n